VLSI integrated circuits ("VLSI chips") are expensive to design, prototype, and test. It is impractical to construct a new VLSI chip simply to test its electrical characteristics or performance. Therefore, VLSI chip designers use computers and computer-aided engineering software to design new VLSI chips, using a high-resolution graphics workstation to display a schematic and physical layout of the VLSI chip. Software is commercially available for simulating electrical performance of complex VLSI chips. This software includes SPICE, originally developed by the University of California, Berkeley as enhanced by HP and described in "HSPICE User's Manual," part number 5955-5528, commercially available from Hewlett-Packard Company, Circuit Technology Group, 5301 Stevens Creek Boulevard, Santa Clara, Calif. 95052 USA. For proper operation SPICE requires input in the form of a SPICE subcircuit data file, known in the art as a "SPICE deck," which numerically describes the location and type of every conductor and component of the VLSI chip. Generation of SPICE decks to describe VLSI circuits is extremely tedious and time-consuming.
One difficult problem faced by VLSI chip designers is design of conductor interconnections between two VLSI chip devices such as transistors. Some conductor interconnects are three-dimensional and follow a non-linear path, since VLSI chips often are constructed with several overlapping layers of metal, polysilicon, and dielectric materials. The electrical characteristics (such as resistance, inductance, and capacitance) of these multilevel interconnects are determined by a complex relationship of numerous physical variables, including metal thickness, insulator thickness, dielectric constant, line width, inter-line spacing, and coupled line length between devices. The relationship between capacitance and interline spacing is non-linear. Also, the variables listed above result in a large number of possible values for resistance, inductance and capacitance depending on the physical size, type, and combination of metals, or insulators selected by the designer.
Accordingly, VLSI circuit designers desire to have a computer system for generating resistance, inductance, and capacitance models for all possible interconnect layout patterns. Since such models for multilevel interconnects require much computation, VLSI circuit designers desire a computer system which can execute such computation in advance in an off-line batch mode.
VLSI chip designers also desire a computer system capable of computing the non-linear relationship of capacitance to interline spacing, given trace width and trace spacing, using polynomial or cubic spline curve fitting and interpolation.
VLSI chip designers further desire a computer system which can quickly generate parameterized SPICE subcircuit data files for interconnects after computing capacitance.
VLSI chip designers also desire a computer system which can interpolate on-chip capacitance values rapidly given the type of integrated circuit ("IC") fabrication process, trace width, and trace spacing, using linear polynomial or cubic spline curve fitting.
VLSI chip designers also desire a computer system which can rapidly generate high-level parameterized SPICE subcircuit and circuit data files based on linear polynomial or cubic spline curve fitting given an IC process, rise time, trace width, trace spacing, and line coupling length.
VLSI chip designers also desire a computer system with an automatically updated spreadsheet display for viewing performance data and for displaying such data in response to variable changes entered by the designer, thereby enabling rapid evaluation of design changes and trade-offs.
When fast clock frequency is used in VLSI chips, transmission line effects will appear on long on-chip interconnects, creating numerous design problems. As is known in the art, signals with 0.5 nanosecond (ns) rise time will incur transmission line effects when the interconnect length is equal to or longer than 3.0 cm. Current VLSI chip die size cannot be dramatically increased due to defect density concerns. Therefore, uniform on-chip interconnect segments to be represented by parameterized subcircuit calls will not approach 3.0 cm for the near future. However, the rise time requirement for full-custom chips will be well below 0.5 nanosecond very soon. Accordingly, VLSI chip designers desire circuit simulators which can import multi-line R, L, C models for lossy, high-density sub-micron interconnect ("SMI") transmission line simulations.
However, the differences between distributed R,C line and transmission line effects indicate that a straightforward extension of conventional R,C line modeling is not enough for on-chip transmission line modeling. Therefore, designers would appreciate a circuit data file generator which can automate the determination of maximum length of each section for on-chip interconnects based on rise time.
To generate SPICE decks, most designers rely on schematic capture programs during pre-layout design and circuit extractors during physical layout. As is known in the art, a SPICE deck is a file of circuit definition data which is fed to the SPICE circuit simulator program. Use of a parameterized model library can relieve designers of all the interconnect modeling and most of the SPICE deck generation effort. Accordingly, designers would appreciate an automated SPICE deck generator for VLSI interconnects which can use parameterized libraries to increase the speed of generating SPICE decks.
Metal materials such as copper, tungsten, or their alloys have been proposed to replace aluminum alloys in some or all metal levels to satisfy future speed, reliability, and manufacturing requirements. Since the metal profiles and resistivities of these proposed metals differ from those of aluminum, interconnect R,C models must be resimulated. Accordingly, circuit designers desire to have a parameterized model library generator to provide accurate and efficient interconnect models for evaluating the impact of material changes on electrical performance.
Signal propagation delays caused by interconnects form a large percentage of total signal delays in VLSI chips. However, for multi-level interconnect technology ("MLIT") modeling in the IC/packaging industry, few CAD tools are available to increase productivity. Three-dimensional structures such as dual signal stripline, via, lead attachments, and trace bends require 3-D numerical simulations for accurate computation of impedance, noise margin and delay. Such simulations are time-consuming and tedious. Therefore, MLIT designers would appreciate accurate and immediate performance information.
High-speed chip designs also demand that engineers consider every combination of technologies from all packaging categories (i.e., IC processes, multilevel interconnect technology ("MCM"), printed circuit boards ("PCB"), via, and lead attachment technologies) to determine which will satisfy chip performance specifications, such as delay and noise margin requirements. A data processing system for interconnect modeling is therefore needed to integrate and optimize chip design and packaging selection.
MLIT designs also require knowledge of material science, electrical engineering, and mechanical engineering. Designers must consider each area of engineering in the search for an optimum design. Therefore, designers would appreciate a data processing system which can assist in evaluating cost-performance trade-offs among all different requirements.